Home > Academics > Academic Units > Faculty of Engineering and Architecture (FoE&A) > Electronics and Electrical Communication Engg. > Santanu Chattopadhyay
Professor
Electronics and Electrical Communication Engg.
Research interest of my group spans over Network-on-Chip Design and Test, Power- and Thermal-Aware Testing of Digital Circuits and Systems, Logic Encryption and Design for Security. Network-on-Chip (NoC) is an embedded System-on-Chip (SoC) design paradigm. In this, functional modules within a chip communicate between themselves using an on-chip router network. Routers with very simple architecture are interconnected either in some regular (such as, mesh, tree topologies), or in a customized fashion. Electrical signal exchanges are replaced by message passing through the network, resolving the issue of bandwidth limitation of bus. This leads to the problems of router architecture design, topology design, power minimization, mapping an application onto such a topology, reconfiguration, ensuring timeliness of tasks etc. Our research works address all these issues. Power and thermal aware test techniques are important for digital systems due to the limited battery life, high power consumption and heat generation during test. Compared to the normal mode of operation, in test mode, power consumption can go up by three times, increasing heat dissipation and creation of thermal hot-spots. Test algorithms and techniques have been developed to address these issues. Both circuit- and system-level solutions have been proposed. Design for Security (DfS) attempts to protect the IP of a design manufactured at third-party foundry. Protection is sought to prevent IP piracy, overproduction, etc. Logic encryption incorporates some key gates into the design. The keys are not available to the manufacturer. Once it comes back to the designer, the keys are provided in tamper-proof memory, thus protecting the IP. Extensive research is being carried out in our group to develop efficient techniques for logic encryption. Finally, we are also working on developing machine learning algorithms to solve EDA problems in VLSI design and test. A number of works in this direction has been initiated ranging from NoC application mapping to low power test.
Additive Cellular Automata Theory and Applications (Volume I) by Chaudhuri P. P., Chowdhury D. R., Nandi S. , Chattopadhyay S. 1-340 (1997)
Compiler Design by Chattopadhyay S. 1-225 (2006)
System Software by Chattopadhyay S. 1-195 (2007)
Compiler Design - Chinese Edition by Chattopadhyay S. 1-196 (2009)
Embedded System Design by Chattopadhyay S. 1-226 (2013)
Network-on-Chip: The Next Generation System-on-Chip Integration by Kundu S., Chattopadhyay S. 1-388 (2014)
Thermal-Aware Testing of Digital VLSI Circuits and Systems by Chattopadhyay S. 1-138 (2018)
Synopsys CAD Laboratory Project Phase II Synopsys Inc.
Kaushik Khatua
Area of Research: Machine learning techniques for VLSI design
